Active matrix liquid crystal display devices are composed of a matrix of liquid crystal pixels arranged horizontally in rows and vertically in columns. The individual liquid crystal picture elements or pixels include first and second opposing polarizers, a liquid crystal material disposed between the polarizers, and transparent electrodes mounted on opposite sides of the liquid crystal material. Individual pixels of active matrix liquid crystal displays are more fully described in U.S. Pat. Nos. 4,632,514; 5,150,235; and 5,161,041, the disclosures of which are incorporated herein by reference.
Electronic matrix arrays find considerable application in active matrix liquid crystal displays. Such active matrix displays generally include X and Y address lines which are vertically and horizontally spaced apart and cross at an angle to one another thereby forming a plurality of crossover points. Associated with each crossover point is an element to be selectively addressed. These elements can be, for example, liquid crystal display pixels or the memory cells of an electronically addressable memory array.
Some form of isolation device (e.g. a thin film transistor) is generally associated with each array element or pixel. The isolation elements permit the individual elements or pixels to be selectively addressed by the application of suitable read potentials between respective pairs of the X and Y address lines.
Amorphous semiconductor thin film field effect transistors or TFTs have found wide usage for the isolation devices in such arrays. Thin film transistors formed from deposited semiconductors such as amorphous silicon alloys are ideally suited for such applications because they exhibit a very high dark resistivity and, therefore, have very low OFF state currents. The reverse leakage currents are so low that very high ON-to-OFF current ratios are made possible for effectively isolating the non-addressed array pixels from the pixels being addressed.
Structurally, thin film transistors (TFTs) generally include substantially co-planar source and drain electrodes, a semiconductor material between the source and drain electrodes, and a gate electrode in proximity to the semiconductor but electrically insulated therefrom by a gate insulator. Current flow through the thin film transistor between the source and drain is controlled by the application of a voltage to the gate electrode. The voltage to the gate electrode produces an electric field which accumulates a charged region near the semiconductor-gate insulator interface. This charged region forms a current conducting channel in the semiconductor through which the device current is conducted.
FIGS. 1 and 2 show a conventional linear-type thin film transistor used in conjunction with an active matrix liquid crystal display. Referring to FIGS. 1 and 2, a plurality (not shown) of TFTs 1 are arranged on a transparent insulating substrate 2 in the form of a matrix. Gate electrodes 3 of the thin film transistors 1 are connected by a gate line 4 extending in the row direction. Drain electrodes 5 of the thin film transistors 1 are connected by a drain line 6 extending in the column direction. A source electrode 7 of each thin film transistor 1 is connected to a transparent pixel electrode 8 independently formed in an area surrounded by the gate and drain lines 4 and 6. The pixel electrode 8 is the transparent electrode adjacent a liquid crystal layer which in conjunction with an opposing electrode on the other side of the liquid crystal layer selectively drives the liquid crystal pixel enabling respective polarizers to transmit or absorb light rays. An electrode, to which a data signal is supplied, will be referred to as a drain electrode hereinafter.
More specifically as shown in FIG. 2, the gate electrode 3 consisting of Cr or the like is formed on the transparent glass substrate 2, and a gate insulating film 9 consisting of silicon oxide or silicon nitride is formed on the upper surface of the glass substrate 2 including the upper surface of the gate electrode 3. A semiconductor film 10 consisting of amorphous silicon is stacked on the gate insulating film 9 above the gate electrode 3. Drain and source electrodes 5 and 7 are formed on the semiconductor film 10. The source and drain electrodes are separated from one another by a predetermined distance, forming channel portion 11. Drain and source electrodes 5 and 7 respectively have contact layers 5a and 7a, and metal layers 5b and 7b, and are electrically connected to the semiconductor film 10.
The source electrode 7 is connected to the transparent pixel electrode 8 consisting of Indium-Tin-Oxide (to be referred to as "ITO" hereinafter) which in turn leads to the pixel made up of a liquid crystal layer, opposing polarizers and opposing electrodes (one being pixel electrode 8).
The linear type thin film transistor of FIGS. 1 and 2, unfortunately, has a relatively high parasitic capacitance which tends to cause pixel flickering, image retention, and gray scale nonuniformity. The relatively high parasitic capacitance (C.sub.GS) of the linear-type TFT shown in FIGS. 1 and 2 causes the pixel voltage across the liquid crystal material to drop by about 1-2 volts when the voltage signal to the gate electrode is shut off. The pixel voltage drop or shift is determined by the following equation: ##EQU1## where C.sub.ST is the storage capacitance, which is added in parallel to the liquid crystal capacitance C.sub.LC. The parameter .delta.V.sub.g is the gate pulse height. .delta.V.sub.p can be offset by adjusting the voltage on the counterelectrode (on the top plate) to get a substantially pure AC voltage across the liquid crystal material. However, because C.sub.LC depends upon the voltage across the liquid crystal material, .delta.V.sub.p can generally not be offset for every gray level and, for large displays, cannot be offset over the entire display area. The residual DC component can lead to pixel flickering, image retention, gray scale nonuniformity and electrochemical degradation of the liquid crystal material.
As the parasitic capacitance of a TFT is decreased, the voltage drop and corresponding DC component across the liquid crystal pixel becomes smaller. Accordingly, the voltage drop across the pixel is proportional to the parasitic capacitance or C.sub.GS of the TFT. The relatively high voltage drop across the prior art pixel discussed above leads to flickering, image retention, and gray scale nonuniformity in the pixel display. Flickering results from a small DC component across the pixel electrodes spanning the liquid crystal layer. Accordingly, pure AC voltage across the pixel electrodes is ideal. By reducing the C.sub.GS, or parasitic capacitance between the gate and source electrodes of a TFT, the DC component across the pixel electrodes of the prior art TFT of FIGS. 1 and 2 can be substantially eliminated or reduced, thereby greatly reducing pixel flickering, gray scale nonuniformity, image retention, and electrochemical degradation of the LC material.
Therefore, there exists a need in the art for a thin film transistor (TFT) having a reduced parasitic capacitance C.sub.GS for use in active matrix liquid crystal displays.
FIGS. 3 and 4 illustrate an attempt, described in U.S. Pat. Nos. 5,003,356 and 5,055,899, to reduce the parasitic or gate-source capacitance C.sub.GS present between the gate and source electrodes. The prior art open-ring thin film transistor of FIGS. 3 and 4 includes a gate electrode 11 formed on a glass substrate 12, and a gate insulating film 13 consisting of silicon nitride and having a thickness of about 3,000 .ANG. stacked on the gate electrode 11. A semiconductor film 14 consisting of amorphous silicon (a-Si) is stacked on the part of the gate insulating film 13 which corresponds to the gate electrode 11. The a-Si layer 14 extends laterally at least to the lateral peripheral edges of the gate electrode 11. A partially circular source electrode 15 is formed on the semiconductor film 14. The source electrode 15 has a diameter of about 4 .mu.m (micrometers).
A drain electrode 16 is formed in a semi-annular or half-circular shape on the semiconductor film 14 only partially surrounding the source electrode 15, thereby forming a semiconductor channel portion "L" in a partially annular space between the source and drain electrodes 15 and 16. Because the channel portion is formed so as to partially surround the source electrode 15, if the distance between the source and drain electrodes is a channel length L, and the length of an arc defined by substantially intermediate points of the channel length L is a channel width W, the channel width W is sufficiently larger than the channel length L. The channel length to width ratio is therefore less than one thereby providing for a reduced parasitic capacitance C.sub.GS. The source electrode 15 is only partially surrounded by the drain electrode 16 because the source and drain electrodes are substantially coplanar and an opening is left in the drain 16 to allow the pixel electrode 19, 25 to extend into electrical contact with the source electrode 15. Furthermore, the open-ring design of the prior art TFT shown in FIGS. 3-4 is provided so as to not unduly limit the viewing display area of the arrayed pixels 19 thereby providing for a fairly large display area for each pixel. The drain electrode 16 of FIGS. 3-4 does not substantially completely surround the source electrode 15.
A plurality (not shown) of the open-ring TFTs 18 of FIGS. 3 and 4 each arranged in the above-described manner are, in the prior art, arrayed on a substrate 12 in the form of a matrix. The source electrode 15 of each thin film transistor 18 is connected to a pixel electrode 19 consisting of a transparent conductive substance such as ITO. Drain electrodes 16 of TFTs 18 arranged in the column direction are commonly connected to a drain line 20, while the gate electrodes 11 of thin film transistors 18 arranged in the row direction are commonly connected to a gate line 21 (each TFT therefore has a gate electrode 11 connected to a horizontally extending gate line 21 and a drain electrode 16 connected to a vertically extending drain line 20. In addition, a plurality (not shown) of pixel electrodes 19 connected to source electrodes 15 of TFTs 18 are arrayed above the glass substrate 12 in the form of a matrix.
A linear portion 25 of the transparent pixel electrode 19 passes through the opening in the semi-circular shaped drain electrode 16. Therefore, the pixel electrode (19, 25) does not cross over the drain electrode 16 but, instead, extends through the opening created in the drain 16. That is, the drain electrode 16 adjacent the linear portion 25 of the pixel electrode is removed so as to prevent an unnecessary electric field from being applied to the channel portion.
In the prior art open-ring TFT of FIGS. 3 and 4, the source electrode 15 is formed so as to be smaller in size than the drain electrode 16. Therefore, the area where the source and gate electrodes 15 and 11 overlap one another is considerably smaller than that where the drain and gate electrodes 16 and 11 overlap one another. Accordingly, the parasitic capacitance, or C.sub.GS, between the gate and source electrodes is decreased.
While the open-ring geometric design of the prior art thin film transistor of FIGS. 3 and 4 does, in fact, reduce the parasitic capacitance between the gate and source electrodes, the open-ring thin film transistor of FIGS. 3-4 is not without its drawbacks. The prior art open-ring TFT is very photosensitive and the parasitic capacitance C.sub.GS of the open-ring TFT shown in FIGS. 3-4 has not been decreased as much as would be most preferably desired. Furthermore, the linear electrode portion 25 and the amorphous silicon semiconductor layer of this TFT are not completely shielded by the gate electrode from the backlighting scheme (not shown) by the gate, thus subjecting the thin film transistor of FIGS. 3-4 to undesirable photosensitivity with respect to the backlighting scheme (not shown) of the liquid crystal display which illuminates the pixels and TFTs from beneath the gate 11. In fact, FIG. 3 illustrates the edges of the semiconductor layer 14 extending beyond the edges of the gate electrode 11. Also, the ON current, an important parameter in determining how fast the pixel will charge up during the positive charging cycle, of this prior art open-ring transistor is undesirably low. Finally, the open-ring TFT shown in FIGS. 3 and 4 is located on the gate line 21, thereby reducing the display area of pixel electrode 19.
The aforesaid described prior art TFTs are very photosensitive. The reason for this high degree of photosensitivity is that the semiconductor a-Si layers are photosensitive and are not completely shielded by the prior art gate electrodes from the intense radiation of backlighting schemes because the prior art a-Si layers extend at least to the periphery of the gate electrodes.
It should be apparent to those skilled in the art that there exists a need in the art for a thin film transistor, in an active matrix liquid crystal display, having a reduced parasitic capacitance, a reduced photosensitivity, a high ON current, and positonable so as to enlarge the display areas of the pixel electrodes.
It is a purpose of this invention to fulfill the above-described needs, as well as other needs apparent to the skilled artisan from the following detailed description of this invention.